The present invention relates to real-time error detection systems and, more particularly, to systems for detecting errors in certain types of encoded binary data.
In the field of digital data error detection, parity error checking schemes are well-known and widely utilized. However, such parity checking schemes generally require the use of an additional parity bit that is added to a string of "1" and "0" bits. Traditionally, the "1" bits are counted in a particular length or string of bits which make up a segment or computer word. If the odd parity system is being utilized, then the number of "1" bits in every computer word must be odd. If the particular coding of a particular computer word provides an even number of "1" bits, a binary "1" parity bit is added. If the particular coding of a particular computer word provides an odd number of "1" bits, then a "0" parity bit is added.
There are many variations of the foregoing scheme for detecting errors, but all have the significant characteristic that bits are added to the data to generate a predictable pattern and the errors are detected as violations of the pattern that is predicted. The added bits are referred to as overhead and an increased overhead increases the bandwidth required to process the data. Therefore, such techniques are not completely desirable.
In U.S. Pat. No. 4,122,441 entitled "Error Detection and Indication System for Bi-Phase Encoded Digital Data", issued Oct. 24, 1978 to Robinson et al, and assigned to the same assignee as the subject application, there is disclosed a real-time error detection system for bi-phase or similarly encoded digital data. Bi-phase or similarly encoded data is characterized by having two transitions in a bit cell for either a binary "1" or a binary "0" value, and one transition in a bit cell for the other binary value. Such encoding inherently generates an even number of transitions corresponding to the binary value represented by the two transitions between each occurrence of the other binary value represented by one transition. Monitoring for the number of transitions of the binary value represented by two transitions provides an indication upon the occurrence of an odd number of transitions. This represents an error condition. The described system utilizes a logic circuit responsive to the binary "1" and binary "0" data clock retrieved from the self-clocking bi-phase encoded data. When an error condition is detected, an error indication signal is generated.
In addition to the bi-phase codes for encoding binary data and which are characterized by having two transitions in a bit cell for a selected binary value, there are a number of codes known as double density such as the one known as Miller in which there is never more than one transition in a given bit cell. Such codes cannot be processed by the error detection system described in said Robinson et al. patent. Because double density codes permit twice the data content in a channel of a given bandwidth than bi-phase codes, extensive use is made of the former. Thus, there is an important need for an error detecting system capable of real-time error detection when applied to double density Miller or similarly encoded binary data.